Digital Computer Arithmetic Datapath Design Using Verilog HDL 电子书下载
This text presents basic implementation strategies for arithmetic datapath designs and methodologies utilized in the digital system. The author implements various datapath designs for addition, subtraction, multiplication, and division. Theory is presented to illustrate and explain why certain designs are chosen. Each implementation is discussed in terms of design choices and how particular theory is invoked in the hardware. Along with the theory that emphasizes the design in question, Verilog modules are presented for understanding the basic ideas that accompany each design. Structural models are implemented to guarantee correct synthesis and for incorporation into VLSI schematic-capture programs. From the modules, the reader can easily add or modify existing code to study current areas of research in the area of computer arithmetic. The emphasis is on the arithmetic algorithm and not the circuit. For any design, both algorithmic and circuit trade-offs should be adhered to when a design is under consideration. Therefore, the idea is to implement each design at the RTL level so that it may be possibly implemented in many different ways (i.e. standard-cell or custom-cell). Thus, professionals, researchers, students, and those generally interested in computer arithmetic can understand how arithmetic datapath elements are designed and implemented. Also included is a CD-ROM which contains the files discussed in the book. The CD-ROM includes additional files utilized in preparing the designs in Verilog including scripts to automatically generate Verilog code for parallel carry-save and tree multipliers. Each Verilog design also contains each module including testbenches to facilitate testing and verification.
尊敬的读者:
欢迎您访问我们的网站。本站的初衷是为大家提供一个共享学习资料、交换知识的平台。每位用户都可以将文件上传至网盘并分享。
然而,随着用户上传的资料增多,我们发现部分不宜或版权问题的书籍被分享到了本站。
为此,我们已经关闭了分享入口,并进行了多次书籍审查,但仍有部分内容未能彻底审查到位。
在此,我们恳请广大读者与我们共同监督,如发现任何不宜内容,请 点击此处 进行举报,我们会第一时间处理并下架相关内容。
希望我们能共建一个文明社区!感谢您的理解与支持!