Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute 电子书下载
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parityВ and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.
尊敬的读者:
欢迎您访问我们的网站。本站的初衷是为大家提供一个共享学习资料、交换知识的平台。每位用户都可以将文件上传至网盘并分享。
然而,随着用户上传的资料增多,我们发现部分不宜或版权问题的书籍被分享到了本站。
为此,我们已经关闭了分享入口,并进行了多次书籍审查,但仍有部分内容未能彻底审查到位。
在此,我们恳请广大读者与我们共同监督,如发现任何不宜内容,请 点击此处 进行举报,我们会第一时间处理并下架相关内容。
希望我们能共建一个文明社区!感谢您的理解与支持!